IBM Debuts World’s First Sub-1 Nanometer Chip Technology
| Source: IBM Newsroom AI
Tags: IBM, semiconductor, nanostack, 7 angstrom, AI hardware, chip design
IBM unveiled the world's first sub-1nm chip at 0.7nm using a new 3D nanostack architecture — packing 100 billion transistors onto a fingernail and projecting 50% more performance or 70% greater energy efficiency over 2nm chips, with AI accelerator throughput potentially reaching 7,000 TOPS vs today's 1,500.
Details
IBM's 0.7nm (7 angstrom) chip marks the first time semiconductor manufacturing has crossed the sub-1nm threshold, a milestone IBM describes as moving computing beyond the nanometer era to the scale of atoms. The key enabling technology is nanostack — a three-dimensional transistor architecture that stacks silicon wafers vertically, effectively unlocking the Z-axis for scaling after 60+ years of two-dimensional progress. The density achievement is concrete: approximately 100 billion transistors on a chip the size of a fingernail, nearly twice the density of IBM's 2nm chip unveiled in 2021. Published projections show 50% more performance or 70% greater energy efficiency compared to that 2nm baseline — a substantial gain over the current leading-edge node. The AI implications are material. IBM estimates a 7-angstrom AI accelerator could reach 7,000 TOPS — roughly 4.7× today's typical 1,500 TOPS — while potentially cutting frontier LLM training time from approximately three months to a few weeks. Structurally, nanostack allows n-type and p-type transistors to stack sequentially rather than side by side, enabling different material combinations per layer to independently optimize power and performance. No commercial deployment timeline was specified.