NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs

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NVIDIA has deployed its Vera CPU at scale in its own electronic design automation (EDA) workflows, the first time the company has shared production performance data for the chip in a real chip design context. Vera is being used to run tools from Cadence and Synopsys — specifically Jasper formal verification and VCS functional simulation — to help design the next generation of NVIDIA processors. Early benchmarks on selected production-class workloads show up to 1.5x performance gains. Vera combines 88 custom NVIDIA Olympus CPU cores with an LPDDR5X memory subsystem and second-generation Scalable Coherent Fabric, targeting high per-core performance and memory bandwidth for sequential, latency-sensitive EDA workloads. This matters because formal verification and logic simulation are among the few remaining chip design stages that resist GPU acceleration. They depend heavily on fast individual cores and low-latency memory access rather than parallelism — making CPU improvements here translate directly to faster design cycles. Compressing EDA throughput shifts products toward manufacturing sooner, tightening NVIDIA's chip release cadence. NVIDIA is clear that the 1.5x figure applies to selected workloads only. Ongoing software optimization work with Cadence and Synopsys — including application profiling and system-level tuning — aims to expand coverage across a broader range of workflows.