Redwood: A Frontier AI Accelerator Designed, Verified, and Deployed from Scratch in 2 Weeks by AI
| Source: arXiv AI
Tags: Redwood, AI chip design, Architect Labs, AI accelerator, recursive self-improvement, FPGA, hardware
Architect Labs built Redwood, the first production-worthy AI accelerator designed end-to-end by an AI system — generating RTL, formal proofs, firmware, and kernels from a 2-human-architect spec in under 2 weeks — achieving 3.4x performance-per-watt versus Jetson Orin Nano, with the deployed chip helping design the next generation.
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Redwood may be the most significant demonstration of AI-driven hardware design to date. Architect Labs provided a high-level specification from two human architects; an AI system autonomously generated the entire stack — performance model, RTL design, UVM verification environments, formal proofs, firmware, and kernel code — in under two weeks with no human intervention below the specification level. Every block reached 95% test coverage via commercial EDA tools, a proprietary formal engine, and hardware-in-the-loop validation.\n\nThe design cycle advantage is as notable as the performance result: specification changes are reverified and redeployed to hardware in under 48 hours, compared to multi-year conventional chip timelines. Redwood Nano, an ultra-low-power FPGA variant, runs multi-billion-parameter models including Llama and Qwen at inference time. Projected onto Samsung 8nm (same process class as Jetson Orin Nano), Redwood delivers 1.75x the throughput at 1.9x lower power — a 3.4x performance-per-watt gain.\n\nThe recursive self-improvement signal: Qwen running on Redwood helped design the next-generation Redwood. The paper explicitly describes this as an early step toward recursive improvement in chip design — the model running on the silicon contributes to designing the next silicon it will run on.\n\nThis collapses the software-to-silicon stack into a single optimization loop. Workload-specific silicon, updated at software cadence, is no longer theoretical.